The programme of the 16th International Conference on Runtime Verification is available on RV 2016 Website.
32nd Annual ACM Symposium on Applied Computing Software Verification and Testing Track
April 3 – 7, 2017, Marrakech, Morocco
* September 15, 2016: Papers and SRC submission
* November 10, 2016: Paper and SRC notification
* November 25, 2016: Camera-ready copies
ACM Symposium on Applied Computing
The ACM Symposium on Applied Computing (SAC) has gathered scientists from different areas of computing over the last thirty years. The forum represents an opportunity to interact with different communities sharing an interest in applied computing.
SAC 2017 is sponsored by the ACM Special Interest Group on Applied Computing (SIGAPP), and will be hosted by the University of Quebec (Montreal, Canada), University Cadi Ayyad (Marrakech, Morocco), Mohamed V University of Rabat – Mohammadia School Of Engineers (Rabat, Morocco) and National School of Applied Sciences (Kenitra, Morocco).
Software Verification and Testing Track
The Software Verification and Testing track aims at contributing to the challenge of improving the usability of formal methods in software engineering. The track covers areas such as formal methods for verification and testing, based on theorem proving, model checking, static analysis, and run-time verification. We invite authors to submit new results in formal verification and testing, as well as development of technologies to improve the usability of formal methods in software engineering. Also are welcome detailed descriptions of applications of mechanical verification to large scale software. Possible topics include, but are not limited to:
– model checking
– theorem proving
– correct by construction development
– model-based testing
– verification-based testing
– symbolic execution
– static and run-time analysis
– abstract interpretation
– analysis methods for dependable systems
– software certification and proof carrying code
– fault diagnosis and debugging
– verification of large scale software systems
– real world applications and case studies applying software verification
Paper submissions must be original, unpublished work. Author(s) name(s) and address(es) must not appear in the body of the paper, and self-reference should be avoided and made in the third person. Submitted paper will undergo a blind review process. Authors of accepted papers should submit an editorial revision of their papers that fits within six two-column pages (an extra two pages, to a total of eight pages, may be available at a charge). Please comply to this page limitation already at submission time. Accepted papers will be published in the ACM SAC 2017 proceedings.
Paper registration is required, allowing the inclusion of papers, posters, or SRC abstracts in the conference proceedings. An author or a proxy attending SAC MUST present the work. This is a requirement for the presented work to be included in the ACM/IEEE digital library. No-show of registered papers, posters, and SRC abstracts will result in excluding them from the ACM/IEEE digital library.
Student Research Competition
As previous editions, SAC 2017 organises a Student Research Competition (SRC) Program to provide graduate students the opportunity to meet and exchange ideas with researchers and practitioners in their areas of interest. Guidelines and information about the SRC program can be found at http://www.sigapp.org/sac/sac2017/.
Program Committee Chairs
Yliès Falcone, Université Grenoble Alpes, Inria, France
Mercedes G. Merayo, Universidad Complutense de Madrid, Spain
Bernhard K. Aichernig, Graz University of Technology, Austria
Ezio Bartocci, TU Vienna, Austria
Marius Bozga, Université Grenoble Alpes, France
Cristiano Braga, Universidade Federal Fluminense, Brazil
Mario Bravetti, Univ di Bologna, Italy
Radu Calinescu, University of York, UK
Ana Cavalli, National Institute of Telecommunications, France
Byoungju Choi, Ewha Womans University, Republic of Korea
Maximiliano Cristi·, Universidad Nacional de Rosario, Argentina
Maria del Mar Gallardo, University of Malaga, Spain
Arie Gurfinkel, Carnegie Mellon University, USA
Tingting Han, University of London, UK
Klaus Havelund, Nasa Jet Propulsion Laboratory, USA
Ralf Huuck, UNSW, Australia
Mohamad Jaber, American University of Beirut, Lebanon
Thierry Jéron, Inria, France
Nikolai Kosmatov, CEA, France
Yves Le Traon, University of Luxembourg, Luxembourg
Yves Ledru, Université Grenoble Alpes, France
Stefan Leue, University of Konstanz, Germany
Mohammad Mousavi, Halmstad University, Sweden
Madhavan Mukund, Chennai Mathematical Institute, India
Shin Nakajima, National Institute of Informatics, Tokyo, Japan
Brian Nielsen, Aalborg University, Denmark
Manuel Nunez, Universidad Complutense de Madrid, Spain
Peter Olveczky, University of Oslo, Norway
Mike Papadakis, University of Luxembourg, Luxembourg
Jun Pang, University of Luxembourg, Luxembourg
Antoine Rollet, Université de Bordeaux, France
Gwen Salaün, Grenoble INP, Inria, France
Gerardo Schneider, University of Gothenburg, Sweden
Adenilso Simao, ICMC/USP, Brazil
Marjan Sirjani, Reykjavik University, Iceland
Marielle Stoelinga, University of Twente, The Netherlands
Jun Sun, Singapore University of Technology and Design
Hélène Waeselynck, CNRS, France
Anton Wijs, Eindhoven University of Technology, The Netherlands
Nina Yevtushenko, Tomsk State University, Russia
Cemal Yilmaz, Sabanci University, Turkey
Fatiha Zaidi, Univ. Paris-Sud, France
The paper entitled “Decentralized Enforcement of Artifact Lifecycles” has been accepted for publication in EDOC 2016, the twentieth Entreprise Computing Conference.
The abstract of the paper is below:
Artifact-centric workflows describe possible executions of a business process through constraints expressed from the point of view of the documents exchanged between principals. A sequence of manipulations is deemed valid as long as every document in the workflow follows its prescribed lifecycle at all steps of the process. So far, establishing that a given workflow complies with artifact lifecycles has mostly been done through static verification, or by assuming a centralized access to all artifacts where these constraints can be monitored and enforced. We present in this paper an alternate method of enforcing document lifecycles that requires neither static verification nor single-point access. Rather, the document itself is designed to carry fragments of its history, protected from tampering using hashing and public-key encryption. Any principal involved in the process can verify at any time that a document’s history complies with a given lifecycle. Moreover, the proposed system also enforces access permissions: not all actions are visible to all principals, and one can only modify and verify what one is allowed to observe.
Following several requests, the deadlines for submitting papers to RV 16 have been extended as follows:
The paper entitled “Modularizing Crosscutting Concerns in Component-Based Systems” has been accepted for publication in SEFM 2016, the 14th International Conference on Software Engineering and Formal Methods.
Below is the abstract of the paper:
We define a method to modularize crosscutting concerns in Behavior Interaction Priority (BIP) component-based framework. Our method is inspired from the Aspect Oriented Programming (AOP) paradigm which was initially conceived to support the separation of concerns during the development of monolithic systems. BIP has a formal operational semantics and makes a clear separation between architecture and behavior to allow for compositional and incremental design and analysis of systems. We thus distinguish local from global aspects. Local aspects model concerns at the component level and are used to refine the behavior of components. Global aspects model concerns at the architecture level, and hence refine communications (synchronization and data transfer) between components. We formalize global aspects as well as their integration into a BIP system through rigorous transformation primitives and overview local aspects. We present AOP-BIP, a tool for Aspect-Oriented Programming of BIP systems, and demonstrate its use to modularize logging, security, and fault-tolerance in a network protocol.
This is joint work with Antoine El-Hokayem (Univ. Grenoble Alpes) and Mohamad Jaber (American University of Beirut).
The paper entitled “Monitoring Multi-threaded Component-based Systems” has been accepted for publication in the proceedings of iFM 16, the 12th International Conference on integrated Formal Methods, June 1st – 5th, 2016, Reykjavik, Iceland.
Below is the abstract of the paper:
This paper addresses the monitoring of logic-independent linear-time user-provided properties on multi-threaded component-based systems. We consider intrinsically independent components that can be executed concurrently with a centralized coordination for multiparty interactions. In this context, the problem that arises is that a global state of the system is not available to the monitor. A naive solution to this problem would be to plug a monitor which would force the system to synchronize in order to obtain the sequence of global states at runtime. Such solution would defeat the whole purpose of having concurrent components. Instead, we reconstruct on-the-fly the global states by accumulating the partial states traversed by the system at runtime. We define formal transformations of components that preserve the semantics and the concurrency and, at the same time, allow to monitor global-state properties. Moreover, we present RVMT-BIP, a prototype tool implementing the transformations for monitoring multi-threaded systems described in the BIP (Behavior, Interaction, Priority) framework, an expressive framework for the formal construction of hetero- geneous systems. Our experiments on several multi-threaded BIP systems show that RVMT-BIP induces a cheap runtime overhead.
This is joint work with Hosein Nazarpour, Saddek Bensalem, Marius Bozga and Jacques Combaz, from Vérimag, Grenoble, France.
A pre-print of the paper can be found here.
One can find the necessary information to download and play with RVMT-BIP by following this link to Hosein’s webpage.
Here is the abstract of the paper:
Runtime enforcement is a verification/validation technique aiming at correcting possibly incorrect executions of a system of interest. In this paper, we consider enforcement monitoring for systems where the physical time elapsing between actions matters. Executions are thus modelled as timed words (i.e., sequences of actions with dates). We consider runtime enforcement for timed specifications modelled as timed automata. Our enforcement mechanisms have the power of both delaying events to match timing constraints, and suppressing events when no delaying is appropriate, thus possibly allowing for longer executions. To ease their design and their correctness-proof, enforcement mechanisms are described at several levels: enforcement functions that specify the input-output behaviour in terms of transformations of timed words, constraints that should be satisfied by such functions, enforcement monitors that describe the operational behaviour of enforcement functions, and enforcement algorithms that describe the implementation of enforcement monitors. The feasibility of enforcement monitoring for timed properties is validated by prototyping the synthesis of enforcement monitors from timed automata.
This is joint work with T. Jéron, H. Marchand, and S. Pinisetty.
Online version at Elsevier can be found here.
A pre-print of the paper can be found here.
The paper entitled “Fully-automated Runtime Enforcement of Component-based Systems with Formal and Sound Recovery” has been accepted for publication in the Springer journal Software Tools for Technology Transfer.
We introduce runtime enforcement of specifications on component-based systems (CBS) modeled in the behavior, interaction and priority (BIP) framework. Runtime enforcement is an increasingly popular and effective dynamic validation technique aiming to ensure the correct runtime behavior (w.r.t. a formal specification) of a system using a so-called enforcement monitor. BIP is a powerful and expressive component-based framework for the formal construction of heterogeneous systems. Because of BIP expressiveness, however, it is difficult to enforce complex behavioral properties at design-time. We first introduce a theoretical runtime enforcement framework for component-based systems where we delineate a hierarchy of enforceable properties (i.e., properties that can be enforced) according to the number of observational steps a system is allowed to deviate from the property (i.e., the notion of k-step enforceability). To ensure the observational equivalence between the correct executions of the initial system and the monitored system, we show that (i) only stutter-invariant properties should be enforced on CBS with our monitors, and (ii) safety properties are 1-step enforceable. Second, given an abstract enforcement monitor for some 1-step enforceable property, we define a series of formal transformations to instrument (at relevant locations) a CBS described in the BIP framework to integrate the monitor. At runtime, the monitor observes and automatically avoids any error in the behavior of the system w.r.t. the property. Third, our approach is fully implemented in RE-BIP, an available tool integrated in the BIP tool suite. Fourth, to validate our approach, we use RE-BIP to (i) enforce deadlock-freedom on a dining philosophers benchmark, and (ii) ensure the correct placement of robots on a map.
Runtime enforcement Component-based systems Monitoring k-step enforceability BIP
Online version at Springer available here.
This is joint work with Mohamad Jaber from American University of Beirut, Lebanon.
I am happy to announce RV 2016 which I will be PC chairing with César Sanchez (IMDEA Madrid, Spain).
This year, RV will be supported by a strong program committee and will take place in a wonderful venue. RV will feature 3 keynote talks from world-class researchers, a summer school on Runtime Verification, a competition on tools for runtime verification, tutorials, and workshops.
Below are the important dates:
- Abstract deadline: May 8, 2016
- Paper and tutorial deadline: May 15, 2016
- Tutorial notification: June 1, 2016
- Paper notification: July 11, 2016
- Camera ready: August 8, 2016
- Summer school on Runtime Verification: September 23-25, 2016
- Workshops and tutorials: September 26-27, 2016
- Conference: September 28-30, 2016
Complete information about RV 2016 can be found at: