Apr 052018
 

VORTEX 2018, ECOOP and ISSTA, Amsterdam, July 16-21, 2018
(https://conf.researchr.org/track/ecoop-issta-2018/vortex-2018-papers)

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Runtime verification (RV) is an approach to software verification concerned with monitoring and analysis of software and hardware under execution. Recently, RV has gained more traction as an effective and promising approach to ensure software reliability, bridging a gap between formal verification and conventional testing; monitoring a system at runtime offers additional opportunities for addressing error recovery, self-adaptation, and other issues that go beyond software reliability. The goal of VORTEX is to bring together researchers working on runtime verification for topics covering either theoretical, or practical aspects, or, preferably, both, with emphasis on object-oriented languages, and systems.

Topics of interest include, but are not limited to, the following ones:

* behavioural types for RV
* combination of static and dynamic analyses
* industrial applications
* language support for RV
* monitor construction and synthesis techniques
* monitoring concurrent/distributed systems
* monitoring oriented programming
* program adaptation
* runtime enforcement, fault detection, recovery and repair
* RV for safety and security
* RV for the Internet of Things
* specification formalisms and formal underpinning of RV
* specification mining
* tool development

Contributions will be formally reviewed by at least three reviewers, and selection will be based on originality, relevance, technical accuracy, and the potential to generate interesting discussions.

Important Dates
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Paper submission: May 16, 2018 23:59 AoE (UTC-12h)
Notification: June 14, 2018

Submission Instructions
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Submissions must be unpublished work, in English, formatted in PDF with acmart sigplan style (http://www.sigplan.org/Resources/Author), and are allowed to be position papers or surveys (max 6 pages), short papers (max 3 pages) presenting preliminary ongoing scientific work, or long papers (max 6 pages) providing more consolidated research contributions.

Papers must be submitted electronically via EasyChair at
https://easychair.org/conferences/?conf=vortex2018 .

Proceedings and Special Issue
—————————–

Accepted papers will, upon agreement by the authors, be published in the ACM Digital Library. Depending on the quality of submissions, authors of selected papers will be invited after the workshop to submit an extended version for a special issue hosted by a prime journal in the field.

Program Committee
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– Davide Ancona, University of Genova, Italy (co-chair)
– Gordon Pace, University of Malta, Malta (co-chair)

– Wolfgang Ahrendt, Chalmers University of Technology, Sweden
– Cyrille Artho, KTH Royal Institute of Technology, Sweden
– Ezio Bartocci, Technische Universität Wien, Austria
– Borzoo Bonakdarpour, Iowa State University, USA
– Ylies Falcone, Univ. Grenoble Alpes, Inria, France
– Klaus Havelund, NASA/Caltech Jet Propulsion Laboratory, USA
– Reiner Hahnle, Technical University of Darmstadt, Germany
– Jean-Baptiste Jeannin, Carnegie Mellon University, USA
– Martin Leucker, University of Lubeck, Germany
– Rumyana Neykova, Imperial College London, UK
– Luca Padovani, University of Turin, Italy
– Antonio Ravara, New University of Lisbon, Portugal
– Giles Reger, University of Manchester, UK
– Gerardo Schneider, University of Gothenburg, Sweden
– Volker Stolz, Hogskulen pa Vestlandet, Norway
– Cesar Sanchez, IMDEA Software Institute, Spain
– Frank S. de Boer, Centrum Wiskunde & Informatica, Leiden University, Netherlands
– Oleg Sokolsky, University of Pennsylvania, USA

Mar 252018
 

We had a successful 2nd School on Runtime Verification in Praz sur Arly, in the beautiful French Alps, organized by the COST action IC1402 Runtime Verification beyond Monitoring (ARVI) and Inria.

Slides of the lectures as well as recorded lecture videos shall be uploaded soon.

Thanks to all lecturers and participants for the passionating lectures and lively discussions.

We are grateful to Inria and our sponsors for permitting the organisation of the school.


 

 

 

Mar 182018
 

The RV Summit in Praz sur Arly near Grenoble, France starts. It will run from March 19 to March 23, 2018.

The RV Summit will feature 2 events:

  • the 2nd ARVI COST School on Runtime Verification on March 19-21,
    co-organized and sponsored by COST Action IC1402 ArVi, Inria and Persyval-Lab;
    School Webpage.
  • an ARVI COST meeting on March 22-23;
    Meeting Webpage.

Dec 112017
 

Today I’m at the defence of Matthieu Renard Ph.D. thesis in Bordeaux, France.

Matthieu’s thesis is entitled Runtime Enforcement of (Timed) Properties with Uncontrollable Events. 

This thesis studies the runtime enforcement of timed properties when some events are uncontrollable. This work falls in the domain of runtime verification, which includes all the techniques and tools based on or related to the monitoring of system executions with respect to requirement properties. These properties can be specified using different models such as logic formulae or automata. We consider timed regular properties, that can be represented by timed automata. As for runtime verification, a runtime enforcement mechanism watches the executions of a system, but instead of just outputting a verdict, it modifies the execution so that it satisfies the property. We are interested in runtime enforcement with uncontrollable events. An uncontrollable event is an event that an enforcement mechanism can not modify. We describe the synthesis of enforcement mechanisms, in both a functional and an operational way, that enforce some desired timed regular property. We define two equivalent enforcement mechanisms, the first one being simple, without considering complexity aspects, whereas the second one has a better time complexity thanks to the use of game theory; the latter being better suited for implementation. We also detail a tool that implements the second enforcement mechanism, as well as some performance considerations. The overhead introduced by the use of our tool seems low enough to be used in some real-time application scenarios.

Dec 072017
 

Today, I’m at the MTV2 day of the French working group on software engineering. The MTV2 day deals with testing methods for verification and validation of software systems.

I’ll present our recent work on Monitoring Decentralised Specifications, which I have also recently presented at ISSTA 2017.

The presented slides can be downloaded by following this link.

The program of the day is available by following this link.

Nov 232017
 

I am at Konstantin Selyunin’s Ph.D. defense in Vienna, Austria.

Konstantin’s thesis is entitled Neural Models For Monitoring and Control with Applications in Automotive Domain.

The abstract of his thesis is below:

Cyber-physical systems (CPS), which incorporate physical as well as computational components, are a grand challenge of academia and industry in terms of their development, verification, and maintenance. In order for CPS to serve their purpose and ultimately make human lives safer, easier, more enjoyable, and convenient, both academia and industry needs to develop new methods for control and monitoring of such systems. Neural models are a very promising and far looking direction for the design of CPS controllers and monitors. In this thesis we first show how neural models can be applied in CPS control to quantify the uncertainty of the system. We then present how digital spiking neural model, called TrueNorth, can be used in the runtime monitoring of temporal-logic specifications for mission-critical systems. In order to be able to deliver not only a qualitative verdict, but also to reason in a quantitative way, we propose an approach for modeling arithmetic-functions with spiking neurones, and implement neural monitors for (signal) temporal logic specifications based on circular convolution.

In the applied part of the thesis we demonstrate how runtime monitoring can speed up the verification and validation phases in automotive electronic development. We identify phases where runtime monitoring can facilitate both pre- and post-silicon verification and testing. To build runtime monitors that are capable of keeping up with the speed of the physical sensors, we developed an approach to convert formalized requirements to hardware monitors, which are then synthesized in an FPGA. The results of this work enable long-term requirements evaluation and foster reuse of the monitors from pre- to post-silicon verification phases using high-level synthesis. We illustrate our approach by formalizing, creating hardware monitors, and evaluating the results in the lab environment for electrical and timing requirements of the industrial SENT and SPC protocols.

Jul 232017
 

CALL FOR PAPERS

***************
Topic E3: Model-based Design and Verification for Embedded Systems
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at DATE 2018,
Dresden, GE
March 19 – 23, 2018
https://www.date-conference.com/call-for-papers#The-Conference
https://www.date-conference.com/group/tpc/members/2018/E3

DATE 2018, will take place from 19 to 23 March, 2018, at the International Congress Center in Dresden, Germany.

The conference addresses all aspects of research into technologies for electronic and embedded systems engineering. An important part of the conference  is devoted to modeling, analysis, design and deployment of embedded software.

We invite you to submit papers to Topic E3: Model-based Design and Verification for Embedded Systems.

Main topics of interest:

Verification techniques for embedded and cyber-physical systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems.

Topic Chair: Petru Eles, Linköping University, SE
Topic Co-Chair: Borzoo Bonakdarpour, University of Waterloo, CA,

Topic Subcommittee Members:

  • Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG
  • Ylies Falcone, University Grenoble Alpes, FR
  • Florence Maraninchi, Verimag, FR
  • Kristin Rozier, Iowa State University, US
  • Lothar Thiele, ETH Zurich, CH

Please note:

Mar 162017
 

We will have a two-day meeting related to the COST Action Runtime Verification beyond Monitoring (ARVI). The purposes of the meeting include:

  • A meeting of the Management Committee (MC).
  • A workshop on contract monitoring.

The program of the meeting can be found here.

My roles during the meeting are twofold:

  • I am representing France in the MC.
  • I am co-chairing the working group related to core runtime verification.

Below is a description of the COST action:

Runtime verification (RV) is a computing analysis paradigm based on observing a system at runtime to check its expected behavior. RV has emerged in recent years as a practical application of formal verification, and a less ad-hoc approach to conventional testing by building monitors from formal specifications.
There is a great potential applicability of RV beyond software reliability, if one allows monitors to interact back with the observed system, and generalizes to new domains beyond computers programs (like hardware, devices, cloud computing and even human centric systems). Given the European leadership in computer based industries, novel applications of RV to these areas can have an enormous impact in terms of the new class of designs enabled and their reliability and cost effectiveness.

EU COST Action IC1402 — project overview at the EU web-site.