Dec 112017

Today I’m at the defence of Matthieu Renard Ph.D. thesis in Bordeaux, France.

Matthieu’s thesis is entitled Runtime Enforcement of (Timed) Properties with Uncontrollable Events. 

This thesis studies the runtime enforcement of timed properties when some events are uncontrollable. This work falls in the domain of runtime verification, which includes all the techniques and tools based on or related to the monitoring of system executions with respect to requirement properties. These properties can be specified using different models such as logic formulae or automata. We consider timed regular properties, that can be represented by timed automata. As for runtime verification, a runtime enforcement mechanism watches the executions of a system, but instead of just outputting a verdict, it modifies the execution so that it satisfies the property. We are interested in runtime enforcement with uncontrollable events. An uncontrollable event is an event that an enforcement mechanism can not modify. We describe the synthesis of enforcement mechanisms, in both a functional and an operational way, that enforce some desired timed regular property. We define two equivalent enforcement mechanisms, the first one being simple, without considering complexity aspects, whereas the second one has a better time complexity thanks to the use of game theory; the latter being better suited for implementation. We also detail a tool that implements the second enforcement mechanism, as well as some performance considerations. The overhead introduced by the use of our tool seems low enough to be used in some real-time application scenarios.

Dec 072017

Today, I’m at the MTV2 day of the French working group on software engineering. The MTV2 day deals with testing methods for verification and validation of software systems.

I’ll present our recent work on Monitoring Decentralised Specifications, which I have also recently presented at ISSTA 2017.

The presented slides can be downloaded by following this link.

The program of the day is available by following this link.

Nov 232017

I am at Konstantin Selyunin’s Ph.D. defense in Vienna, Austria.

Konstantin’s thesis is entitled Neural Models For Monitoring and Control with Applications in Automotive Domain.

The abstract of his thesis is below:

Cyber-physical systems (CPS), which incorporate physical as well as computational components, are a grand challenge of academia and industry in terms of their development, verification, and maintenance. In order for CPS to serve their purpose and ultimately make human lives safer, easier, more enjoyable, and convenient, both academia and industry needs to develop new methods for control and monitoring of such systems. Neural models are a very promising and far looking direction for the design of CPS controllers and monitors. In this thesis we first show how neural models can be applied in CPS control to quantify the uncertainty of the system. We then present how digital spiking neural model, called TrueNorth, can be used in the runtime monitoring of temporal-logic specifications for mission-critical systems. In order to be able to deliver not only a qualitative verdict, but also to reason in a quantitative way, we propose an approach for modeling arithmetic-functions with spiking neurones, and implement neural monitors for (signal) temporal logic specifications based on circular convolution.

In the applied part of the thesis we demonstrate how runtime monitoring can speed up the verification and validation phases in automotive electronic development. We identify phases where runtime monitoring can facilitate both pre- and post-silicon verification and testing. To build runtime monitors that are capable of keeping up with the speed of the physical sensors, we developed an approach to convert formalized requirements to hardware monitors, which are then synthesized in an FPGA. The results of this work enable long-term requirements evaluation and foster reuse of the monitors from pre- to post-silicon verification phases using high-level synthesis. We illustrate our approach by formalizing, creating hardware monitors, and evaluating the results in the lab environment for electrical and timing requirements of the industrial SENT and SPC protocols.

Jul 232017


Topic E3: Model-based Design and Verification for Embedded Systems

at DATE 2018,
Dresden, GE
March 19 – 23, 2018

DATE 2018, will take place from 19 to 23 March, 2018, at the International Congress Center in Dresden, Germany.

The conference addresses all aspects of research into technologies for electronic and embedded systems engineering. An important part of the conference  is devoted to modeling, analysis, design and deployment of embedded software.

We invite you to submit papers to Topic E3: Model-based Design and Verification for Embedded Systems.

Main topics of interest:

Verification techniques for embedded and cyber-physical systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems.

Topic Chair: Petru Eles, Linköping University, SE
Topic Co-Chair: Borzoo Bonakdarpour, University of Waterloo, CA,

Topic Subcommittee Members:

  • Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG
  • Ylies Falcone, University Grenoble Alpes, FR
  • Florence Maraninchi, Verimag, FR
  • Kristin Rozier, Iowa State University, US
  • Lothar Thiele, ETH Zurich, CH

Please note:

Mar 162017

We will have a two-day meeting related to the COST Action Runtime Verification beyond Monitoring (ARVI). The purposes of the meeting include:

  • A meeting of the Management Committee (MC).
  • A workshop on contract monitoring.

The program of the meeting can be found here.

My roles during the meeting are twofold:

  • I am representing France in the MC.
  • I am co-chairing the working group related to core runtime verification.

Below is a description of the COST action:

Runtime verification (RV) is a computing analysis paradigm based on observing a system at runtime to check its expected behavior. RV has emerged in recent years as a practical application of formal verification, and a less ad-hoc approach to conventional testing by building monitors from formal specifications.
There is a great potential applicability of RV beyond software reliability, if one allows monitors to interact back with the observed system, and generalizes to new domains beyond computers programs (like hardware, devices, cloud computing and even human centric systems). Given the European leadership in computer based industries, novel applications of RV to these areas can have an enormous impact in terms of the new class of designs enabled and their reliability and cost effectiveness.

EU COST Action IC1402 — project overview at the EU web-site.

Nov 292016

SAC-SVT 2017

Software Verification and Testing 2017
A Track of the ACM Symposium on Applied Computing

Marrakech, Morocco, April 3 – 7, 2017


For the past thirsty years, the ACM Symposium on Applied Computing has been a primary gathering forum for applied computer scientists, computer engineers, software engineers, and application developers from around the world. SAC 2017 is sponsored by the ACM Special Interest Group on Applied Computing (SIGAPP), and will be hosted by the University of Quebec (Montreal, Canada), University Cadi Ayyad (Marrakech, Morocco), Mohamed V University of Rabat – Mohammadia School Of Engineers (Rabat, Morocco) and National School of Applied Sciences (Kenitra, Morocco).
Symposium on Applied Computing been a primary gathering forum for applied computer scientists, computer engineers, software engineers, and application developers from around the world over the past thirty years.
The Software Verification and Testing track aims at contributing to the challenge of improving the usability of formal methods in software engineering. The track covers areas such as formal methods for verification and testing, based on theorem proving, model checking, static analysis, and run-time verification. These areas include a broad range of topics, but are not limited to:

  • Model checking
  • Theorem proving
  • Correct by construction development
  • Model-based testing
  • Verification-based testing
  • Symbolic execution
  • Static and run-time analysis
  • Abstract interpretation
  • Analysis methods for dependable systems
  • Software certification and proof carrying code
  • Fault diagnosis and debugging
  • Verification of large scale software systems
  • Real world applications and case studies applying software verification

Registration Information

Please note the following important dates regarding registration.

Author Registration

Friday, December 16, 2016

Early Registration

Friday, February 3, 2017


1 day during April 3 – 7, 2017


For authors. Paper registration is required, allowing the inclusion of the paper/poster in the conference proceedings. An author or a proxy attending SAC MUST present the paper: This is a requirement for the paper/poster to be included in the ACM/IEEE digital library. No-show of scheduled papers and posters will result in excluding them from the ACM/IEEE digital library.

Accepted Papers

The following papers were accepted by the SAC-SVT 2017 Programme Committee.

  • Mohamed Amine Aouadhi, Benoît Delahaye and Arnaud Lanoix.
    Moving from Event-B to Probabilistic Event-B
  • Huu-Vu Nguyen and Tayssir Touili.
    CARET Model Checking For Pushdown Systems
  • Rudolf Ramler, Thomas Wetzlmaier and Claus Klammer.
    An Empirical Study on the Application of Mutation Testing for a Safety-Critical Industrial Software System 
  • Thibaud Antignac, Mukelabai Mukelabai and Gerardo Schneider.
    Specification, Design and Verification of an Accountability-Aware Surveillance Protocol
  • Davide Basile, Felicita Di Giandomenico and Stefania Gnesi.
    Statistical Model Checking of an Energy-Saving Cyber-Physical System in the Railway Domain
  • Jeongho Kim and Eunseok Lee.
    History-based Test Case Prioritization for Failure Information
  • Yunus Kiliç and Hasan Sözer.
    Generating Runtime Verification Specifications based on Static Code Analysis Alerts
  • Pedro Delgado-Pérez, Inmaculada Medina-Bulo, Sergio Segura, Antonio García-Domínguez and Juan José Domínguez-Jiménez.
    GiGAn: Evolutionary Mutation Testing for C++ Object-Oriented Systems
  • András Márki and Birgitta Lindström.
    Mutation Tools for Java

Venue and Travel Information

Information about the venue and how to travel to Marrakesh is available on SAC 2017 Website at: