Today, I’ll be co-chairing the Software Verification and Testing track at the the 33rd ACM/SIGAPP Symposium On Applied Computing.
The program is available at this link.
VORTEX 2018, ECOOP and ISSTA, Amsterdam, July 16-21, 2018
Runtime verification (RV) is an approach to software verification concerned with monitoring and analysis of software and hardware under execution. Recently, RV has gained more traction as an effective and promising approach to ensure software reliability, bridging a gap between formal verification and conventional testing; monitoring a system at runtime offers additional opportunities for addressing error recovery, self-adaptation, and other issues that go beyond software reliability. The goal of VORTEX is to bring together researchers working on runtime verification for topics covering either theoretical, or practical aspects, or, preferably, both, with emphasis on object-oriented languages, and systems.
Topics of interest include, but are not limited to, the following ones:
* behavioural types for RV
* combination of static and dynamic analyses
* industrial applications
* language support for RV
* monitor construction and synthesis techniques
* monitoring concurrent/distributed systems
* monitoring oriented programming
* program adaptation
* runtime enforcement, fault detection, recovery and repair
* RV for safety and security
* RV for the Internet of Things
* specification formalisms and formal underpinning of RV
* specification mining
* tool development
Contributions will be formally reviewed by at least three reviewers, and selection will be based on originality, relevance, technical accuracy, and the potential to generate interesting discussions.
Paper submission: May 16, 2018 23:59 AoE (UTC-12h)
Notification: June 14, 2018
Submissions must be unpublished work, in English, formatted in PDF with acmart sigplan style (http://www.sigplan.org/Resources/Author), and are allowed to be position papers or surveys (max 6 pages), short papers (max 3 pages) presenting preliminary ongoing scientific work, or long papers (max 6 pages) providing more consolidated research contributions.
Papers must be submitted electronically via EasyChair at
Proceedings and Special Issue
Accepted papers will, upon agreement by the authors, be published in the ACM Digital Library. Depending on the quality of submissions, authors of selected papers will be invited after the workshop to submit an extended version for a special issue hosted by a prime journal in the field.
– Davide Ancona, University of Genova, Italy (co-chair)
– Gordon Pace, University of Malta, Malta (co-chair)
– Wolfgang Ahrendt, Chalmers University of Technology, Sweden
– Cyrille Artho, KTH Royal Institute of Technology, Sweden
– Ezio Bartocci, Technische Universität Wien, Austria
– Borzoo Bonakdarpour, Iowa State University, USA
– Ylies Falcone, Univ. Grenoble Alpes, Inria, France
– Klaus Havelund, NASA/Caltech Jet Propulsion Laboratory, USA
– Reiner Hahnle, Technical University of Darmstadt, Germany
– Jean-Baptiste Jeannin, Carnegie Mellon University, USA
– Martin Leucker, University of Lubeck, Germany
– Rumyana Neykova, Imperial College London, UK
– Luca Padovani, University of Turin, Italy
– Antonio Ravara, New University of Lisbon, Portugal
– Giles Reger, University of Manchester, UK
– Gerardo Schneider, University of Gothenburg, Sweden
– Volker Stolz, Hogskulen pa Vestlandet, Norway
– Cesar Sanchez, IMDEA Software Institute, Spain
– Frank S. de Boer, Centrum Wiskunde & Informatica, Leiden University, Netherlands
– Oleg Sokolsky, University of Pennsylvania, USA
We had a successful 2nd School on Runtime Verification in Praz sur Arly, in the beautiful French Alps, organized by the COST action IC1402 Runtime Verification beyond Monitoring (ARVI) and Inria.
Slides of the lectures as well as recorded lecture videos shall be uploaded soon.
Thanks to all lecturers and participants for the passionating lectures and lively discussions.
We are grateful to Inria and our sponsors for permitting the organisation of the school.
The RV Summit in Praz sur Arly near Grenoble, France starts. It will run from March 19 to March 23, 2018.
The RV Summit will feature 2 events:
We are happy to announce our Springer LNCS tutorial book, Lectures on Runtime Verification – introductory and advanced topics, co-edited by Ezio Bartocci and myself.
The book is available on Springer Website.
The book contains introductory and advanced lectures on Runtime Verification authored by members of the COST Action IC 1402, ArVi, Runtime Verification beyond Monitoring.
The book contains the following chapters:
Today I’m at the defence of Matthieu Renard Ph.D. thesis in Bordeaux, France.
Matthieu’s thesis is entitled Runtime Enforcement of (Timed) Properties with Uncontrollable Events.
This thesis studies the runtime enforcement of timed properties when some events are uncontrollable. This work falls in the domain of runtime verification, which includes all the techniques and tools based on or related to the monitoring of system executions with respect to requirement properties. These properties can be specified using different models such as logic formulae or automata. We consider timed regular properties, that can be represented by timed automata. As for runtime verification, a runtime enforcement mechanism watches the executions of a system, but instead of just outputting a verdict, it modifies the execution so that it satisfies the property. We are interested in runtime enforcement with uncontrollable events. An uncontrollable event is an event that an enforcement mechanism can not modify. We describe the synthesis of enforcement mechanisms, in both a functional and an operational way, that enforce some desired timed regular property. We define two equivalent enforcement mechanisms, the first one being simple, without considering complexity aspects, whereas the second one has a better time complexity thanks to the use of game theory; the latter being better suited for implementation. We also detail a tool that implements the second enforcement mechanism, as well as some performance considerations. The overhead introduced by the use of our tool seems low enough to be used in some real-time application scenarios.
Today, I’m at the MTV2 day of the French working group on software engineering. The MTV2 day deals with testing methods for verification and validation of software systems.
I’ll present our recent work on Monitoring Decentralised Specifications, which I have also recently presented at ISSTA 2017.
The presented slides can be downloaded by following this link.
The program of the day is available by following this link.
I am at Konstantin Selyunin’s Ph.D. defense in Vienna, Austria.
Konstantin’s thesis is entitled Neural Models For Monitoring and Control with Applications in Automotive Domain.
The abstract of his thesis is below:
Cyber-physical systems (CPS), which incorporate physical as well as computational components, are a grand challenge of academia and industry in terms of their development, verification, and maintenance. In order for CPS to serve their purpose and ultimately make human lives safer, easier, more enjoyable, and convenient, both academia and industry needs to develop new methods for control and monitoring of such systems. Neural models are a very promising and far looking direction for the design of CPS controllers and monitors. In this thesis we first show how neural models can be applied in CPS control to quantify the uncertainty of the system. We then present how digital spiking neural model, called TrueNorth, can be used in the runtime monitoring of temporal-logic specifications for mission-critical systems. In order to be able to deliver not only a qualitative verdict, but also to reason in a quantitative way, we propose an approach for modeling arithmetic-functions with spiking neurones, and implement neural monitors for (signal) temporal logic specifications based on circular convolution.
In the applied part of the thesis we demonstrate how runtime monitoring can speed up the verification and validation phases in automotive electronic development. We identify phases where runtime monitoring can facilitate both pre- and post-silicon verification and testing. To build runtime monitors that are capable of keeping up with the speed of the physical sensors, we developed an approach to convert formalized requirements to hardware monitors, which are then synthesized in an FPGA. The results of this work enable long-term requirements evaluation and foster reuse of the monitors from pre- to post-silicon verification phases using high-level synthesis. We illustrate our approach by formalizing, creating hardware monitors, and evaluating the results in the lab environment for electrical and timing requirements of the industrial SENT and SPC protocols.
The list of papers accepted at the Software Verification and Testing track at SAC 2018 is out and available at:
Thanks to all the track members for their thorough reviews and in-depth discussions of the papers.
Thanks to all authors for their submissions.
SAC 2018 will be held in Pau, France April 9 – 13, 2018.
I’m at ISSRE 2017 in Toulouse, France, for the presentation of our paper on Interactive Runtime Verification and attending the talks of the day.
Our paper on Interactive Runtime Verification (i-RV) can be downloaded here.
Verde, our open-source tool for i-RV, can be retrieved and experimented with our interactive tutorial by following this link. Our interactive tutorial illustrates how i-RV can be used to more effectively debug C programs leveraging runtime verification.